1. Field of the Invention
The present invention relates to an active matrix display apparatus using an electro-luminescence element (hereinafter, referred to as EL element) which emits light by injecting a current for an image display, and a driving method of the same. Hereinafter, in the present specification, the active matrix display apparatus using the EL element is referred to as an EL panel.
2. Description of the Related Art
Active Matrix Display Apparatus
FIG. 4 illustrates an overall configuration example of a color EL panel. The color EL panel shown in the figure includes a column control circuit 3, a column register 5, a row register 6, and a control circuit 9 in addition to a display region 2 in which a pixel circuit 1 including a display element (EL element) and its drive circuit is two-dimensionally arranged.
In the display region 2, a plurality of pixel circuits 1 is arranged in a matrix pattern along a row direction and a column direction. The pixel circuit 1 performs acquiring and storing of a display signal and driving of the EL element. When a pixel circuit has such a function, this display apparatus is referred to as an active matrix display apparatus.
Each pixel circuit 1 is connected with a signal line 4 and a scanning line 7 of the column corresponding to the pixel circuit. Each of the pixel circuits 1 of the row corresponding thereto acquires the display signal supplied to the corresponding signal line 4 all at once in accordance with a control signal (scanning signal) of the scanning line 7(row selection period). When the next scanning signal is activated, the display element contained in each pixel circuit 1 is lighted with luminance corresponding to the acquired display signal (lighting period). The pixel circuits 1 are divided into three sets having the display elements corresponding respectively to one of three primary colors RGB to attain a color display.
The scanning signal of each scanning line 7 is generated by a row register 6 having register blocks provided to the respective rows, to each of which register blocks a row clock KR and a row scan start signal SPR are input. The display signals of the respective columns, which are supplied to each signal line 4, are generated by the column control circuits 3 provided to the respective columns. The column control circuits 3 are divided into three sets corresponding respectively to the display elements of the three primary colors RGB, each arranged every three columns. The column control circuit 3 of each column supplies a desired display signal to the signal line 4 of each column in accordance with a video signal VIDEO and a sampling signal SP as well as a horizontal control signal 8. A control circuit 9 is input with a horizontal sync signal SC corresponding to the video signal VIDEO 9, and generates a horizontal control signal 8. The sampling signal SP is generated by a column register 5 including the registers of one third of the number of the column control circuit 3. The column register 5 is input with a column clock KC and a column scanning start signal SPC as well as a horizontal control signal 8 which is used mainly for a reset operation of the column register 5.
Pixel Circuit
The pixel circuit 1 of a current writing type is commonly adopted, such a type being hard to be affected by a variation of characteristics of a TFT (thin film transistor) to be used therein. In this case, the display signal supplied to the signal line 4 is a current signal. The pixel circuit 1 of the display panel commonly includes the TFT. Since the TFT has a large variation in characteristics, the current writing type which is hard to be affected by the variation of characteristics is often used.
FIGS. 5 and 6 are configuration examples of the pixel circuit of a current writing type (referred to also as “current programming method”) disclosed in U.S. Pat. Nos. 6,373,454 and 6,661,180. The pixel circuit 1 shown in the Figures has an EL element (EL in the Figures) which is the display element and a drive circuit of the EL element. The drive circuit, in the examples of the Figures, includes switching transistors (hereinafter, referred to as transistor) M1, M2, and M4 each made of an n-type TFT, a drive transistor M3 made of a p-type TFT, and a capacitor (capacitor or storage capacitor) C1.
The pixel circuit 1 is connected with an emission power source line PVdd, a signal line data for supplying a current Idata, and two scanning lines P1 and P2 for supplying the scanning signals, and performs a current writing operation and a lighting operation through the drive circuit of the EL element. The EL element has an anode terminal (current injection terminal) connected to the emission power source line PVdd (first power source) through a transistor M4 and a drive transistor M3 and a cathode terminal connected to a ground line (second power source) CGND.
FIG. 7 illustrates a time chart of each scanning signal of the scanning lines P1 and P2.
First, at the time of the current writing operation (Row selection period T1), each scanning signal of the scanning lines P1 and P2 becomes P1=H level, P2=L level, respectively, and the transistors M1 and M2 are turned on, and the transistor M4 is turned off. Then, a drain terminal of the drive transistor M3 is isolated from the current injection terminal (anode terminal in the examples of FIGS. 5 and 6) of the EL element through the transistor M4. In this state, the drive transistor M3 is connected to the signal line data through a gate terminal thereof, and the gate terminal and the drain terminal of the drive transistor M3 are short-circuited, thereby the transistor being put into a diode-connection state. As a result, a gate voltage decided by the characteristic of the drive transistor M3 is generated due to the current Idata supplied to the signal line data so as to charge the storage capacitor C1 between the gate terminal and the source terminal.
Next, at the time of the lighting operation (lighting period T2), each scanning signal of the scanning lines P1 and P2 becomes P1=L level and P2=H level, respectively, and the transistors M1 and M2 are turned off, and the transistor M4 is turned on. Then, the drive transistor M3 is connected to the current injection terminal (anode terminal in the examples of FIGS. 5 and 6) of the EL element through the drain terminal thereof. In this state, the gate terminal of the drive transistor M3 is isolated from the signal line data so that the transistor M3 is put into a released state, and therefore, at the time of the current writing operation time, the voltage charged into the storage capacitor C1 between the gate terminal and the source terminal reaches a gate voltage of the transistor M3 as it is. As a result, the current flowing into the drive transistor M3 becomes substantially the current Idata of the signal line data, and therefore, the EL element can light with light emission luminance corresponding to the current Idata.
When the pixel circuit 1 shown in FIG. 5 is actually formed on the substrate as a display panel, each pixel circuit 1, as shown in FIG. 8, is accompanied with parasite capacitances cx1 and cx4 caused by wiring cross of the scanning lines P1 and P2 and the signal line data. In a high definition display panel, a top emission method is common, in which light is taken out from a surface of the pixel circuit 1. Hence, the signal line data overlaps with a cathode transparent electrode layer formed on the whole surface of a display region, in the region overlapping with the anode electrode of the EL element and the region not overlapping with the anode electrode, and therefore, each of the parasite capacitances cx2 and cx3 is accompanied. In addition to this, the signal line data is accompanied with a capacitance cx5 between a control terminal (gate terminal) of the transistor M2 and a main conductive terminal (source or drain terminal).
The parasitic capacitance accompanied with the signal line data of each column is a sum total of the parasitic capacitances accompanied with the pixel circuit of each column. The parasitic capacitance value accompanied with this signal line depends on a panel size and the number of displays. For example, in the display panel of three inches-480 columns, the capacitance value becomes approximately 5 pF. Even in the pixel circuit of FIG. 6, the parasitic capacitance value accompanied with this signal data becomes also approximately 5 pF.
However, the current writing operation of the pixel circuit shown in FIGS. 5 and 6 is significantly affected by the parasitic capacitance value. The signal current completes the programming within the writing period through charging or discharging the parasitic capacitance of the signal line in addition to the storage capacitance of the pixel. Consequently, a current writing operation ability (PRG ability) is shown conceptually by the following formula (1).“PRG ability”=“write current”×“write time”÷“signal line parasitic capacitance”  (1)
When the “PRG ability” value is not secured, the current writing operation becomes insufficient, and the display image quality is remarkably damaged.
As shown in the formula (1), when the write current in low luminance is small, the PRG ability becomes small. The signal line parasitic capacitance is almost decided by the number of display rows and the display size, but the drastic reduction beyond the same is difficult. The write time is also restricted by the time decided from the number of displayed rows and a refresh rate.
The drive current injected into the EL element is decided by the brightness of the EL element, and therefore, the drive current cannot be set large without any restriction. Hence, the writing current cannot be set large also. When the light emission duty is set small and an instant brightness of the EL element is set large, the write current can be also set large. However, when the current is set large, this causes a problem that deterioration of the brightness of the EL element is accelerated.